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CppCon 2017: Chandler Carruth “Going Nowhere Faster”

CppCon · 113.3K views · 2017-11-02 · 1:00:58

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Overview

Chandler Carruth shows how to squeeze more performance out of already-optimized C++ code, covering how the CPU executes it. The talk goes into pipelining, branch prediction and speculative execution using benchmarks.

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Recommended as the best presentation on how modern CPUs run code, and why speculative execution matters for performance.

Recommended by 2 HN people across 3 months · HN mentions 2017–2026

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What people said

inetknght · 2026-04 · Strong recommendation

The best presentation I've seen about CPU performance related to pipelining, branch prediction, and speculative execution was Chandler Carruth's "Going Nowhere Faster" presentation at CppCon 2017 [0]. I do recommend watching the whole presentation, but if you watch nothing else then just watch the 5 minutes or so from the linked timestamp. [0]: [VIDEO]

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pkaye · 2018-11 · Recommendation

Chandler Carruth has a good talk with an example of why speculative execution is critical for performance. [VIDEO] It starts around 36m13s time frame.

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inetknght · 2017-12 · Recommendation

Disclaimer: I am not an expert and have not measured. This is armchair theory. But, I would argue two things. First, the former appears to have at least one unaligned arithmetic: > 400538: mov 0x200b01(%rip),%rdx # 601040 <counter> ...while the latter's equivalent instruction is 4-byte aligned: > 40057d: mov 0x200abc(%rip),%rdx # 601040 <counter> So, I would argue that's the biggest source of _speedup_ in the second case. However, I'm really interested in whether that's true since I don't see a memory fence; so the memory should be in L0 cache for both cases; I have trouble believing that an unaligned access can be so much slower with the data in cache. As for the `callq` to `repz retq`, I would venture a guess that the CPU's able to identify that there are no data dependencies there and the data's never even stored; I'd argue that it probably never even gets executed because the instruction should fit in instruction cache and branch prediction cache and all. Arguably. Like I said, I'm not an expert. I'd say run it through Intel's code analyzer tool. [LINK] Tangential video worth watching: [VIDEO] Edit: actually, thinking about it, it's not unaligned access , it's unaligned math . I don't think that should affect performance at all? Fun.

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