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The Mill CPU Architecture - the Belt (2 of 13)

Mill Computing, Inc. · 37.7K views · 2013-07-29 · 1:26:50

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Overview

The second talk in the Mill CPU series by Mill Computing, covering the Belt, the Mill's operand-passing model that replaces general registers. It explains the cost of register renaming in conventional wide CPUs and how the Belt reaches high instruction-level parallelism.

On Hacker News

HN points to the Mill talks as an excellent, deep look at an unconventional CPU design, especially in threads on registers and instruction sets.

Recommended by 1 HN people across 1 months · HN mentions 2013–2023

Topics

Computer architecture & CPUs
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mill cpubeltregister renaminginstruction setcomputer architecture

What people said

wood_spirit · 2023-12 · Recommendation

This is reminiscent of the Mill CPU which had temporal addressing and called the history a “belt”. the Mill was described in an excellent series of talks: [VIDEO]

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riazrizvi · 2017-01 · Criticism

According to the CTO, 80% of software operations are loops ( [VIDEO] )? I need convincing of that before I watch the rest of the talk. I suspect it would be a fundamental premise for the architecture of the chip. If it's not true, the stats are probably skewed for an unusual benchmark.

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w0000t · 2015-08 · Reference

No ordinary registers. Instead you have a FIFO queue( belt ), where every element( register ) is accessible and has a relative address( offset ). [VIDEO]

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Sources

Video by Mill Computing, Inc., played through YouTube.

Data and selection notes

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HN Library: HackerTube export (2026-10-31) and open-index/hacker-news. Upstream summaries and classifications may contain AI errors.

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