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Experiences Building Edge TPU with Chisel

Chisel · 10.5K views · 2018-11-17 · 37:47

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Overview

A Google talk from the Chisel community in which engineers recount designing the Edge TPU with the Chisel hardware construction language. It covers the productivity gains and the problems they hit.

On Hacker News

Pointed to as a rare first-hand account of a real, shipping ASIC built in an open-source HDL, useful in HDL and FPGA choice discussions.

Recommended by 1 HN people across 1 months · HN mentions 2019–2025

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What people said

therealcamino · 2023-02 · Recommendation

Google had a really interesting talk on their experiences with Chisel in designing the first Edge TPU chip. A lot of the issues are specific to industrial chip design, where verification and coverage are essential, but many would apply to small-scale personal designs as well. A good overview of the advantages as well as the problems. And many of the problems would apply to other front ends, which are essentially using Verilog as the target language. [VIDEO]

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walterbell · 2025-05 · Reference

Google TPU engineers used open-source Chisel for ASIC design (2018), [VIDEO] "Google Edge TPU devices" , 100 comments (2019), [LINK] & [LINK] "Coral Edge TPU review" , 100 comments (2020), [LINK] "TPU transformation: 10 years of our AI-specialized chips" , 60 comments (2024), [LINK]

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ekiwi · 2021-07 · Reference

It was in fact the EdgeTPU (which is different from the TPU used in data centers). The talk from a google engineer can be found on youtube: [VIDEO] Please note that they were using a version of Chisel from 5+ years ago and many things have changed since then. It is still true though that Chisel can be hard to learn for typical hardware engineers, which is why it may be best suited for small and highly dedicated teams rather then large hardware companies. [EDIT] Here is a talk from a solo-developer using the latest version of Chisel: [LINK]

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